1. Field of the Invention
The present invention relates to a semiconductor memory device and, particularly, to a semiconductor memory device which has a redundancy circuit and is capable of performing a preliminary test of the redundancy circuit.
2. Description of the Related Art
With the recent tendency of miniaturization, high integration and large capacity of semiconductor memory device, it has been very difficult to obtain complete semiconductor memory devices having no defect. That is, almost all semiconductor memory devices include defective memory cell, defective word line and/or defective bit line. In order to ship such semiconductor memory device having defects as an acceptable semiconductor memory device, it is usual to provide a redundancy circuit within the semiconductor memory device.
A redundancy method using a fuse has been known as a remedy for defect of the semiconductor provided with the redundancy circuit. That is, a memory cell array of the semiconductor memory device is tested to investigate address or addresses containing defect or defects and, when an address containing defect is input, a fuse within a redundancy address program circuit is preliminarily cut off so that a redundancy memory cell array is selected and used. In such redundancy system, however, it is impossible to select the redundancy circuit unless the fuse is cut off. That is, it is impossible to preliminarily test the redundancy memory cell array. Therefore, the redundancy memory cell array can be tested only after the defective memory cell array is replaced by the redundancy memory cell array. Therefore, when it is found that there is a defect in the replaced redundancy memory cell array, the latter must be replaced inefficiently by another redundancy circuit. In view of this inefficiency, a method for preliminarily testing a redundancy memory cell array before the fuse in the redundancy address program circuit is cut off has been proposed in, for example, Japanese Patent Application Laid-open No. He 5-36297. In the proposed method, a redundancy memory cell array can be tested before a fuse is cut off by providing, in addition to a fuse for programming such that a redundancy memory cell array is selected and used, another fuse for a redundancy circuit test and a gate circuit, etc.
However, in the method disclosed in the Japanese Patent Application Laid-open No. He 5-36297, it is necessary to additionally provide a fuse and a gate, etc., in every redundancy address program circuit, resulting in that a chip area is increased. Therefore, a semiconductor memory device having a small chip area and having a redundancy circuit which can be tested preliminarily has been highly requested.